In many communication systems, data is streamed from one device to another without an accompanying clock signal. During the transmission, the signals carrying the data streams may become jittery and difficult to decipher and process by the receiving device. Therefore, many systems utilize clock and data recovery circuits (CDR) to retime the incoming signals carrying the data streams and transmit the retimed signals to the receiving device. This requires the CDR to generate a clock that locks to the frequency of the streamed data. In many systems, the CDR detects the frequency of the incoming signals and phase aligns the clock signal to the incoming signals. The incoming signal is then retimed with a clean clock that has been generated by the CDR. The retimed signal then may be output to the receiving device for further processing.